A phase-locked loop (PLL) synthesizer is an electronic system that translates an input reference-frequency signal to an output signal at a different frequency. Specifications such as output frequency range, step size, stability, tuning speed, and power characterize the breadth of a particular synthesizer design. Measurements of spectral purity such as harmonic and spurious signal suppression, and phase noise levels indicate how closely the synthesizer approaches ideal operation. Trade-offs exist between many different design parameters. As just one example, tuning speed, i.e. how fast the output frequency can be changed, may have to be sacrificed to reduce spurious signals.
FIG. 1 is a simplified block diagram for a conventional PLL frequency synthesizer. The circuit is based on a voltage controlled oscillator (VCO) whose frequency output is locked in relation to a reference frequency by a feedback loop. In the figure, voltage controlled oscillator 125 generates an output signal 135 at frequency f. A portion of this signal is fed back to phase detector 110 via power splitter 130 and frequency divider 140. The frequency divider has a division ratio of N, meaning that its output frequency is N times less than its input frequency. The other input to the phase detector is a reference frequency signal 105 FREF which may be generated by a high-stability, fixed-frequency oscillator, for example. The phase detector compares the two signals at its inputs and generates an error signal which is then fed through low pass loop filter 115 and amplifier 120 before reaching the voltage controlled oscillator. (The phase detector, low pass filter, amplifier, VCO, power splitter and frequency divider therefore form a loop circuit.) The filtered and amplified error signal changes the frequency of the VCO until f is locked in relation to FREF by: f=FREF×N. If frequency divider 140 is programmable, as is often the case, the synthesizer can be programmed to generate any one of many frequencies within a range determined by the VCO. The step size between the possible output frequencies is equal to the reference frequency FREF.
Phase noise is a manifestation of instability of the output frequency of a PLL synthesizer and is observed as random frequency fluctuations around the desired output frequency. It is a limiting factor in the sensitivity of radio frequency receivers. The level of phase noise near the desired carrier frequency depends on phase noise in the reference signal and on the PLL synthesizer circuit design.
Synthesizer phase noise within the loop filter bandwidth is given by λ=λPD+20 log N where λPD is the cumulative phase noise of the reference signal, phase detector, feedback divider, loop filter and amplifier referred to the phase detector input, and N is the division ratio of the frequency divider. In practice, the synthesizer phase noise performance is usually limited by large division ratios required to provide high-frequency output with fine resolution. For example, to obtain 1 MHz frequency resolution at 10 GHz output, the feedback divider ratio is 10,000, corresponding to 80 dB phase noise degradation.
At high frequencies an additional fixed divider (pre-scaler) may be needed as programmable dividers are often limited to lower frequency operation. This increases the total division ratio by the pre-scaler division ratio resulting in further phase noise degradation. (The amplitudes of spurious signals at multiples of the reference frequency also tend to be proportional to N.)
FIG. 2 is a simplified block diagram for a conventional PLL frequency synthesizer with frequency conversion in the synthesizer feedback loop. The circuit shown in FIG. 2 represents a conventional approach to phase noise reduction in PLL synthesizers based on reducing the frequency division ratio in the feedback loop. In the figure, voltage controlled oscillator (VCO) 225 generates an output signal 235 at frequency f. A portion of this signal is fed back to phase detector 210 via power splitter 230, mixer 250, and frequency divider 240. The other input to the phase detector is a reference frequency signal 205 FREF which may be generated by a high-stability, fixed-frequency oscillator, for example. A digital-to-analog converter (DAC) 260 is provided to translate digital tuning commands 255 for coarse tuning.
Mixer 250 reduces the maximum frequency division ratio by mixing the VCO output frequency with offset frequency f1. Therefore, when the PLL synthesizer of FIG. 2 is locked, f=f1±fREF×N. Offset frequency f1 may be obtained from another phase-locked loop or frequency multiplier.
Circuits of the type shown in FIG. 2 sometimes suffer from false lock to spurious mixer products. For example, the PLL might lock to the wrong sideband, harmonics, intermodulation products or leakage of the local oscillator. An accurate coarse-tuning mechanism is required to avoid false lock problems. In FIG. 2, DAC 260 tunes VCO 225 to approximately the correct frequency before the phase-locked loop locks. For such a coarse tuning system to work well, the tuning characteristics of the VCO must be linear and repeatable. Precise calibration is required to compensate for VCO temperature drift. DAC's are usually noisy and adversely affect synthesizer phase noise performance if they are not properly removed from the circuit after initial frequency acquisition.
Further, in the design of FIG. 2, mixer harmonic and intermodulation products can fall within the synthesizer loop bandwidth as shown in FIG. 3. FIG. 3 shows a spurious mixer product within the low pass filter response of the loop filter. Fractional-N and direct digital synthesis architectures can have similar problems with elevated spur levels.
What is needed is a PLL synthesizer capable of generating high frequency signals with low phase noise, low spurious emissions and fine frequency resolution.